1. Technical Field
The present invention relates to a memory device, and more particularly, to a method of controlling a read operation of a memory device.
2. Discussion of the Related Art
With the development of semiconductor manufacturing technology, a system-on-chip (SOC), in which a plurality of system chips are integrated into a single chip, has been proposed. The SOC typically includes a memory that stores an operating system (OS) program or data that is generated when the OS program is executed.
In general, a memory includes a memory cell array having a matrix structure. The memory receives a row address signal, a column address signal, and a data read control signal or a data write control signal from a memory controller. The memory outputs data of a corresponding memory cell or writes data to a corresponding memory cell in response to the data read control signal or the data write control signal. Furthermore, the memory reads or writes data in synchronization with a memory clock signal received from the memory controller. The memory controller receives a system clock signal and generates the memory clock signal. The system clock signal is used in the memory controller and a system including the memory controller while the memory clock signal is used only in the memory. The system corresponds to an SOC including the memory controller and the memory.
An example of a memory controller that generates a memory clock signal from a system clock signal and provides the memory clock signal to a plurality of memories is disclosed in U.S. Pat. No. 5,630,096, entitled “Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order”.
FIG. 1 is a block diagram of a conventional memory controller 10 and a memory 20. Referring to FIG. 1, the memory controller 10 includes a central processing unit (CPU) 11 and a memory interface 12 connected to the memory 20. The CPU 11 and the memory 20 are also connected to a data bus 30.
A method of controlling a read operation of the memory 20 with the conventional memory controller 10 will now be explained with reference to FIGS. 1 and 2. FIG. 2 is a timing diagram of signals used in the read operation of the memory 20.
In FIG. 2, a row address signal RADD, a column address signal CADD, and a pre-charge control signal PGN are required for the reading of a memory cell of the memory 20. A memory clock signal MCLK is identical to a system clock signal SCLK.
Referring to FIG. 2, a time interval “D1”, during which a sense amplifier control signal SEN is enabled, must be longer than a time interval “C” required for an effective data signal to be output from a memory cell. Furthermore, to output the effective data signal from the memory cell, a cell transistor must allow a sufficient cell current to flow. For this purpose, a wordline WL1 connected to a gate of the cell transistor must be sufficiently activated to reach a set voltage level.
As a time interval “E” required for the wordline WL1 to be sufficiently activated to reach the set voltage level increases, the interval “C” increases. Consequently, a time interval required for a bit line sense amplifier to amplify a data signal to evaluate a data value also increases. As a result, the interval “E” has the largest effect on the read operation of the memory 20.
As further shown in FIG. 2, the time interval “E” appears in a time interval “A1”, during which the row address signal is shifted, but does not appear in a time interval “A2”, during which the row address signal is not shifted. Thus, a read speed of the memory 20 is reduced more during the interval “A1” than the interval “A2”. Accordingly, when the memory 20 must operate at a high frequency erroneous data may be output. For example, when the frequency of the memory clock signal MCLK is increased during the interval “A1”, an enable interval of a chip select signal CSN becomes shorter. Thus, a time interval “B1” and the time interval “D1” also become shorter. However, the interval “E” is not varied but is uniformly maintained so that the interval “C” becomes longer than the interval “D1”. Consequently, the memory 20 outputs erroneous data.
To prevent the memory 20 from outputting erroneous data when operating at a high frequency, a conventional memory interface divides the system clock signal SCLK to generate a memory clock signal MCLK having a frequency lower than the frequency of the system clock signal SCLK, as shown in FIG. 3. Accordingly, the enable interval of the chip select signal CSN is longer and the interval “E” required for the wordline WL to be sufficiently activated and the interval “C” required for an effective data signal to be output from the memory cell can be secured. In a system in which the read operation of the memory 20 is frequently executed, however, the performance of the system deteriorates as the frequency of the memory clock signal MCLK decreases.